Frequency synthesizers are widely used in communication devices, mobile communication terminals, and high-frequency integrated circuits used for the mobile communication terminals in order to generate a high-frequency communication carrier. FIG. 1 is a block diagram showing a configuration of a common frequency synthesizer. The frequency synthesizer shown in FIG. 1 is a PLL frequency synthesizer including a voltage controlled oscillator (VCO) 200, a frequency divider 910, a phase comparator and charge pump 220, and a loop filter 230. An oscillation frequency of the voltage controlled oscillator (VCO) 200 is controlled by a control voltage output by the loop filter 230. The voltage controlled oscillator 200 outputs a high-frequency clock signal fvco. The clock signal fcvo can be used as a high-frequency communication carrier. The frequency divider 910 frequency-divides the high-frequency clock signal fvco. The phase comparator and charge pump 220 includes a phase comparator that compares the frequency and the phase of the clock signal frequency-divided by the frequency divider 910 with those of a reference clock used as a reference, and a charge pump circuit that charges or discharges electrical charge based on a result of comparison by the phase comparator. The loop filter 230 smoothes the electrical charge charged or discharged by the charge pump to generate the control voltage for controlling the oscillation frequency of the voltage controlled oscillator (VCO) 200. With this configuration, as the clock signal output by the frequency divider 910, a signal of a desired frequency in phase with the reference clock can be obtained. Further, by forming the frequency divider of a variable frequency circuit and changing a frequency division ratio, the clock signal fvco output by the voltage controlled oscillator VCO can be set to a desired frequency.
In the configuration of the frequency synthesizer, each of the voltage controlled oscillator 200 and the frequency divider 910 operates at a high frequency. Thus, large power is consumed. Further, in recent years, an upper limit frequency for use has been increased to accommodate multiple bands and bandwidth expansion in wireless communications. Thus, frequency synthesizers consume larger power. On the other hand, in order to operate communication devices and mobile communication terminals in particular for a long period of time and to further reduce the sizes of the terminals by reducing battery sizes thereof, reduction of power consumption of entire transmitter/receiver circuits and the frequency synthesizers are demanded.
Patent Document 1 describes a PLL circuit that consumes low power and accommodates a wide oscillation frequency range. FIG. 2 is a block diagram of the PLL circuit (frequency synthesizer) described in Patent Document 1. Among components of the PLL circuit in FIG. 2, a voltage controlled oscillator 200, a frequency divider 911, a first phase comparator 921, a charge pump 922, and a filter 230 substantially correspond to the components in the frequency synthesizer described in FIG. 1. In addition to these components, the PLL circuit in FIG. 2 includes a second phase comparator 923 and a current control circuit 924. The second phase comparator 923 obtains a phase difference between a clock signal fDIV frequency-divided by the frequency divider 911 and a reference clock signal fREF using a period of time longer than that for the first phase comparator 921, by temporal averaging. The current control circuit 924 controls an operating current of the frequency divider 911, based on a result of comparison using the second phase comparison circuit 923. According to the configuration in FIG. 2, it is detected whether or not the PLL circuit has entered into a stable locked state by the second phase comparator, and the operating current of the frequency divider 911 is reduced when the PLL circuit has entered into the stable locked state. Power consumption of the frequency divider can be thereby reduced.
FIG. 3 shows an internal configuration of the frequency divider 911 described in Patent Document 1. The frequency divider 911 is constituted from a fixed frequency divider 912 that receives and frequency-divides an oscillation signal fvco of the voltage controlled oscillator, a prescaler 913 that further frequency-divides the frequency obtained by frequency division by the fixed frequency divider 912 to reduce the frequency, and a programmable counter 914 that is a variable frequency divider. An output signal of the programmable counter 914 is phase compared with the reference clock by the phase comparator. A control input terminal 915 is provided at the fixed frequency divider 912 that operates at a highest speed among these components, and the operating current can be controlled by the current control circuit 924.
A ½ frequency divider constituted from a combination of a plurality of differential latch circuits is used for a circuit that operates at a high frequency, such as the fixed frequency divider 912. A traditional differential latch circuit 900 is shown in FIG. 4, and a ½ frequency divider using differential latch circuits 900 is shown in FIG. 5. The differential latch circuit shown in FIG. 4 includes a differential pair (M1, M4) that constitute a data input unit, a holding unit (M2, M3), a current source 930, and load resistances R11 and R12. Data signals received from data terminals D and Db are latched in synchronization with clock signals received from clock terminals Ck and Ckb to be output from data output terminals Q and Qb.
The ½ frequency divider 990 shown in FIG. 5 is a frequency divider in which clock signals supplied from clock terminals Ck and Ckb are ½ frequency-divided by two differential latch circuits 900-1 and 900-2 in FIG. 4 to be output from data output terminals Q and Qb. Since the differential latch circuit shown in FIG. 4 and the ½ frequency divider shown in FIG. 5 operate in a differential manner, a high-speed operation is possible. A latch circuit and a frequency divider corresponding to the differential latch circuit in FIG. 4 and the ½ frequency divider in FIG. 5 are described in Patent Document 2.    [Patent Document 1]    JP Patent Kokai Publication No. JP2008-205601A, which corresponds to US Patent Application Publication No. US2008/0197897A1.    [Patent Document 2]    JP Patent Kokai Publication No. JP2007-116257A